Computer chip performance has recently encountered physical limits imposed by the available space on integrated circuits. Researchers now propose building chips upward as a potential solution. This method could extend or surpass the Moore’s Law prediction from the 1960s, which anticipated that transistor counts on chips would double every two years at constant cost. Greater transistor numbers typically increase processing capability, yet manufacturers face shrinking space and difficulties in further miniaturization. The new approach stacks chips vertically using standard silicon while maintaining near-equivalent performance levels. Scientists at the University of Illinois Urbana-Champaign indicate that the technique may boost computing density and speed, lower energy use through better efficiency, and shorten connections. One researcher noted that six transistors on a flat surface currently store one bit, but vertical layering allows distribution across multiple planes, reducing space needs and improving inter-layer communication. Earlier chip-stacking efforts encountered heat issues during fabrication at around 1,000 degrees Celsius, which would damage prior layers. Separate baking or heat-resistant materials reduced performance, density, and integration compared with the monolithic method described. The team addressed thermal constraints using junctionless transistors with adjusted chemical compositions processed before stacking, plus ultra-thin flexible silicon nanomembranes applied at under 200 degrees Celsius. These membranes conform to surfaces and reduce defects common in rigid wafer bonding. The process uses single-crystalline silicon, achieves high yields, and appears scalable for commercial production. Experiments reached three layers with functional logic and memory circuits, demonstrating viability while allowing future increases in layer count. Remaining hurdles include higher operating voltages that require further refinement, though vertical designs should ultimately improve energy efficiency. Classical chips remain essential despite quantum advances. The lead researcher stated that additional layers beyond three can maintain high transistor performance with strong yields and consistency. The work offers a basis for industrial transfer and was published in Nature.
