IBM announced on June 25 a significant advance in semiconductor design. The company presented what it calls the first sub-1 nanometer chip technology, built with a transistor structure at the 0.7 nm or 7 angstrom scale. Officials described the step as important because conventional chip scaling now faces physical limits.
Jay Gambetta, Director of IBM Research, stated that the development moves computing past the nanometer scale into atomic dimensions. He noted that the new nanostack architecture does not simply shrink transistors but redesigns chip construction to increase power and energy efficiency.
Semiconductors remain essential across computing, household devices, communications, transport, and infrastructure. Gambetta added that the work extends IBM’s record of advancing future technologies and prepares the ground for the coming phase of computing.
The sub-1 nm chip contains roughly 100 billion transistors within a fingernail-sized area, nearly doubling the density of IBM’s 2 nm chip from 2021. The design relies on structural and material changes, notably the three-dimensional nanostack layout. The company indicated that performance and efficiency improvements remain achievable even at these reduced sizes.
IBM projects up to 50 percent higher performance and 70 percent better energy efficiency than its 2 nm technology. These gains could benefit generative AI, cloud systems, and future electronic devices.
Researchers developed the nanostack transistor architecture, described as the first three-dimensional nanosheet-based design. It stacks transistors vertically through sequential integration, allowing more devices per chip and the use of varied materials in each layer to tune performance and power separately.
